![]() ![]() – Verilog RTL & Gate Performance Optimizations Hereare some key features of”ModelSimSE”: The bes standards and platform support in the industrymake it easy to adopt in the majority of process and toolflows. The combination of industry-leading, native SKSperformance with the best integrated debug and analysis environmentmake ModelSim the simulator of choice for both ASIC and FPGAdesigns. Mentor Graphics was the first to combine single kernel simulator(SKS) technology with a unified debug environment for Verilog,VHDL, and SystemC. ![]() The created library of ModelSim is compatible withall the platforms which means you can simulate your design in anyplatform. Once theworking library is created the next step is to compile the designunits into it. All the designsare compiled into the library and the user start the new designsimulation in ModelSim by creating a library which is called work.Work is the default library name used by the compiler. ModelSim is a tool for simulation andverification for Verilog, VHDL and system Verilog. ![]()
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